The present invention relates generally to the manufacture of integrated circuit devices and, in a preferred embodiment thereof, more particularly relates to surface planarization techniques used in conjunction with such manufacture.
The manufacture of integrated circuit devices is basically a layering process in which successively applied insulative coatings are used to encapsulate and separate two or more "tiers" of metal electrical interconnect structures which are conductively joined at selected locations thereon to collectively define the overall electronic circuitry of the device. Each tier of metal interconnect structures is typically adhered to, and follows the contour of, an outer side surface of a coating (usually an insulative coating) which overlies the previously applied interconnect tier.
Due to the nonplanar topography of each interconnect tier, the outer side surface of the insulative coating directly overlying and contacting the tier has a highly irregular contour normally defined by a spaced apart series of relatively deep depressions positioned adjacent relatively flat, higher topography sections of the coating surface which are positioned over relatively thick components of the underlying interconnect tier. These deep surface depressions are highly undesirable since, if left as they are, they would create sharp bends in the subsequently added metal interconnect portions which are ultimately positioned over the depressions. Accordingly, it is now a common practice in the manufacture of integrated circuit devices to "planarize" the coating surface in which these deep depressions exist prior to continuing the insulation/conductor layering process needed to complete the overall device.
Such surface planarization, which functions to generally fill in and level off the coating surface depressions, is conventionally carried out in a variety of manners utilizing a siloxane based spin-on glass (SOG) material as a filler. For example, one previously proposed surface planarization method entails the steps of depositing over the entire insulative coating surface an SOG coating which is then hot plate baked and nitrogen furnace cured before being back etched to remove essentially all of the SOG coating except those portions disposed within and filling the previously existing surface depressions.
This surface planarization method is undesirable for various reasons. For example, the hot plate bake/nitrogen furnace curing process is not sufficient to essentially completely convert the siloxane structure of the SOG to a desirable silicate, quartz-like structure. Additionally, such pouring process often leaves a portion of the solvents used to manufacture the SOG material in place within the surface depressions. This remaining solvent tends to corrosively attack metal interconnect structures contacting the portions of the SOG coating remaining after etch back. Moreover, the incomplete curing of the SOG coating undesirably reduces its adherence to coatings subsequently applied thereon.
In an attempt to solve these problems, a final curing process, utilizing oxygen plasma, has relatively recently been proposed and has been incorporated in the previously described surface planarization method after the nitrogen furnace cure and before the SOG etch back. While this addition of oxygen plasma final curing of the SOG coating tends to solve the aforementioned problems, it creates one of its own-namely, the creation of relatively large cracks in the portions of the SOG coating remaining in the surface depressions after etch back. This SOG crackage undesirably results in a high rejection rate for the finished devices.
One recently proposed surface planarization method which tends to avoid this SOG cracking includes the step of utilizing highly specialized equipment to initially deposit SOG only into the coating surface depressions, thereby eliminating the need for SOG coating etch back. Under this method the initially deposited "pockets" of SOG filling the previously existing surface depressions are sequentially subjected to a hot plate baking process and a final oxygen plasma cure. This surface planarization process, while producing satisfactory end results, is inordinately expensive (due to the specialized SOG curing equipment required) and is thus not commercially feasible.
From the foregoing it can readily be seen that a need exists for an improved, commercially feasible surface planarization method for use in the manufacture of integrated circuit devices. It is accordingly an object of the present invention to provide such a method.